1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to an operation method of non-volatile memory.
2. Description of Related Art
Electrically erasable programmable read-only memory (EEPROM) is a non-volatile memory wherein data can be written, read, or erased repeatedly, and the data stored in an EEPROM remains even when the power supply is turned off. Thus, EEPROM has become broadly applied to personal computers and other electronic apparatuses.
Presently, a non-volatile memory having a charge storage layer of silicon nitride is provided. Such silicon nitride charge storage layer usually has respectively a silicon oxide layer on the top and at the bottom, so as to form a memory cell of silicon-oxide-nitride-oxide-silicon (SONOS) structure. When voltages are supplied to the control gate and the source region/drain regions of the device to program the device, hot electrons are produced in the channel region and close to the drain region and are injected into the charge storage layer. The electrons injected into the charge storage layer are not distributed evenly in the entire charge storage layer, instead, the electrons stay in a particular area in the charge storage layer and present Gaussian distribution in the direction of the channel, thus, leakage current won't be produced easily.
However, when fabricating a SONOS memory, the gate of a SONOS memory cell in the memory cell region and the gate of a transistor in the logic circuit region are usually formed within the same step, and the oxide/nitride/oxide (ONO) layer of the SONOS memory cell and the gate oxide of the transistor in the logic circuit region are then patterned right after the gates are formed. However, since the thicknesses and structures of the oxide/nitride/oxide layer of the SONOS memory cell and the gate oxide of the transistor in the logic circuit region are very different, the thickness of the gate oxide becomes thinner and thinner along with the minimization of the device. Thus, it is very difficult to completely pattern the oxide/nitride/oxide layer of the SONOS memory cell and to prevent the substrate surface of the logic circuit region from being over-etched and producing recess. To resolve the foregoing problems, the SONOS memory cell in the memory cell region and the transistor in the logic circuit region are fabricated separately, and which complicates the fabricating process.